FIG. 1 illustrates a sensor including a matrix array of active pixels and a read circuit according to the prior art.
The matrix array MPA comprises a plurality (9 in the example of the figure, several thousand in most actual cases) of active pixels PX that are generally produced in CMOS (complementary metal-oxide-semiconductor) technology, said pixels being arranged in rows and columns; the columns are identified by the references C1, C2 and C3. Each pixel comprises a photodiode that generates electrical charge when it is illuminated by light; the photodiode accumulates, during what is called an integration time, the generated charge, that it is then possible to read directly or via an intermediate storage node.
The matrix array is read like a random-access memory: all the pixels of a given column are connected to the same read conductor (LC1 for column C1; LC2 for column C2; LC3 for column C3); a row-selecting signal (not shown) selects a single pixel for each column, which transfers a voltage representative of the accumulated charge to the read conductor of the corresponding column.
At the foot of each column, a respective sample-and-hold circuit (not shown in FIG. 1; referenced SH in FIG. 3A) acquires the voltage on the read conductor and converts it to digital format with a ramp-type converter. In the simplest embodiment, the voltage signal acquired by the sample-and-hold circuit is delivered to a first input of an analog comparator (CMP1 for column C1, CMP2 for column C2, CMP3 for column C3) which receives, on its second input, a voltage ramp SR that is common to a plurality of columns and that exceeds, at the end of the conversion, the sampled voltages on the conductors LC1, LC2, LC3, etc. The binary output signal of the comparator (SBC1, SBC2, SBC3) switches when the ramp SR is equal to the voltage present on the first input of the comparator. Thus a voltage-to-delay conversion is obtained. Other voltage-to-delay converting architectures exist and may be applied to the analog-digital conversion of signals generated by a matrix-array sensor.
In this configuration, a clock signal H drives a Gray-code counter CCG that is common to all the columns (Gray code is preferred to natural binary code because it is more robust with respect to errors due to the appearance of transient states; however, use of a natural binary code, or any other type of binary code, is also possible) in order to perform a count that starts at the same time as the voltage ramp, or with a known and controllable temporal offset (in FIG. 1, a double-headed arrow symbolizes the synchronization between the ramp generator GR and the Gray-code counter CCG). In a manner known per se, the synchronization may be achieved via a digital sequencer that sends start signals simultaneously (or with a preset offset) to the ramp generator and to the counter. The Gray code generated by the counter CCG is propagated to a bank of registers with parallel inputs and series outputs, R1, R2, R3—one bank per column. The switching of each output signal of a comparator—SBC1, SBC2, SBC3—triggers the sampling of the value of the counter to the corresponding register. Thus, each register stores the Gray code generated at the moment at which the voltage ramp common to all the comparators was equal to the voltage signal corresponding to the column of pixels with which it is associated.
The set of components made up of the sample-and-hold circuits, the comparators, the registers and, optionally, the ramp generator, the Gray-code counter and/or the clock-signal generator is referred to as the read circuit CL.
The read circuit of the image sensor of FIG. 1 has a simple structure that consumes little power and is easy to implement. The result of the analog-digital conversion is monotonic, has a good linearity and a low dispersion from column to column. Its drawback is that it is difficult to obtain both a good conversion resolution (for example, 14 bits) and a high acquisition rate (faster than 10 μs). Specifically, for a resolution of 14 bits, it is necessary to count up to 16384. If the clock signal has a frequency of 400 MHz, this requires about 41 μs. Decreasing conversion time by a factor of 8—which would allow an acquisition rate of about 1 image/5 μs—would require the clock frequency to be multiplied by 8 (3.2 GHz), this being impossible, or in any case not possible with the electronic technologies used to produce active matrix-array sensors. In addition, when clock frequency is increased, it becomes difficult to propagate the Gray code synchronously over required distances which may be large (several millimeters) if the number of columns of the matrix is high.
An alternative structure uses a separate (Gray or natural binary) counter for each column. This does not allow the rate of acquisition of images to be significantly increased, because it is still necessary to generate a high clock frequency and to propagate it synchronously over a large distance.
These architectures are described in document U.S. Pat. No. 7,880,662.
Document EP 2 221 975 describes a circuit for reading a sensor including a matrix array of active pixels, said circuit comprising a local clock for each column. As the clock signal need not be propagated, its frequency may be higher. In contrast, this circuit implements a complex mechanism in order to prevent synchronization errors in the synchronization of the various local clocks.
The invention aims to overcome the drawbacks of the prior art. More particularly, it aims to provide a read circuit allowing a high image-acquisition rate to be achieved without sacrificing conversion resolution and via means that are simpler than those employed in the circuit of the aforementioned document EP 2 221 975.
According to the invention, this aim is achieved by using a clock that is common to the various columns, referred to as the primary or reference clock, having a relatively low frequency, and local frequency multipliers at the foot of each column, which generate what are called secondary, or local, clock signals that drive respective counters. Only the primary clock must be propagated and, as it has a relatively low frequency, this poses no particular difficulty. The use of frequency multipliers driven by a common primary clock allows the synchronization of the secondary clock signals to be ensured. Moreover, according to one advantageous embodiment of the invention, the counting may be carried out by modified natural binary counters in which the least significant bit follows the secondary clock, instead of switching on each falling or rising front, allowing a counting rate that is double the clock frequency to be achieved. This allows a gain of a factor of two in the rate of acquisition of the images or of one bit of conversion resolution for a given rate.